1. Field of the Invention
The present invention relates to a semiconductor storage device that is used as an image display buffer memory and that is accessed asynchronously by a CPU (central processing unit) and a display device, for example.
2. Description of the Related Art
Conventionally, a driver controller that drives an organic EL (electronic luminescence) device or TFT-LCD (thin-film transistor liquid crystal display) or the like uses a dual port memory as an image processing memory for the reasons outlined below.
(1) The writing of image data to the driver controller and the reading of display data are implemented simultaneously.
(2) The power consumption of portable devices such as cellular phones must be reduced and, hence, access is made to an image processing memory by using asynchronous access or a low-speed clock. That is, a high-speed clock cannot be used.
(3) The CPU-system clock speed is different from image processing-system clock speed. Thus, timing conversion is required.
Japanese Patent Application Kokai (Laid Open) No. 2002-108690 discloses a multi-port memory device that intends to secure a large port number and suppress the power consumption by a simple constitution. This multi-port memory device does not have complex arbitration means.
This multi-port memory device fixes the timing of access and the access order to the DRAM (Dynamic Random Access Memory) for each system in one cycle of the sequence operation, performs serial-parallel conversion in sync with the write request timing by two serial-parallel conversion circuits, and temporarily stores the converted signals in the write buffers associated with the respective serial-parallel conversion circuits.
Also, data that are read from the DRAM are temporarily stored in two read buffers, converted to serial data by the parallel-serial conversion circuits associated the respective read buffers, and then supplied to outside after being delayed by a delay adjustment circuit to match the read request timing. In addition, the multiport memory device of Japanese Patent Application Kokai No. 2002-108690 separately supplies an operation clock to each system and stops the supply of the operation clock for a stopped system.
Japanese Patent Application Kokai No. 2001-101861 discloses a semiconductor storage device that aims to implement user-friendly multiple port functions with a reduced circuit scale.
This semiconductor storage device has a port expansion circuit that creates a first clock signal that corresponds with a clock signal supplied to a first input port for a single-port RAM (Random Access Memory) and a second clock signal with timing that is delayed with respect to the first clock signal. The port expansion circuit also produces a third clock signal from a clock signal that is supplied from the second input port. This port expansion circuit causes first and second latch circuits to retain address signals and data that are supplied from the address terminal and data input terminal of the second input port in accordance with the third clock signal. An address signal supplied via an address terminal of the first input port upon generation of the first clock signal is sent to the address terminal of the RAM, and a read signal from the selected memory cell is transmitted from the data output terminal. The writing is done when the address signal retained in the first latch circuit and write data held in the second latch circuit are sent to the address terminal of the RAM and the data input terminal in response to the second clock signal.
The multiport memory device of Japanese Patent Application Kokai No. 2002-108690 requires, for each system, a serial-parallel conversion circuit, a parallel-serial conversion circuit and a delay adjustment circuit. Accordingly, simplification of the circuitry can hardly be attained. In the semiconductor storage device of Japanese Patent Application Kokai No. 2001-101861, the first port is dedicated to the reading and the second port being is dedicated to the writing. Thus, this semiconductor storage device is not a full dual-port configuration.